An Investigation of Quaternary [5,3] Error Correcting Codes and their Implementation with Binary Devices

Authors

  • A.K.M. Toyarak Rian Department of Mathematics and Physics, North South University
  • Partha Pratim Dey Department of Mathematics and Physics, North South University
  • Farzana Karim Elora Department of Mathematics and Physics, North South University

DOI:

https://doi.org/10.26713/jims.v7i1.248

Keywords:

Linear code, Generator matrix, Equivalent code, Gates

Abstract

In this paper we investigate the existence, equivalence and some other features of quaternary error correcting codes. We also discuss the binary hardware devices that could be used to code and decode messages when these error correcting codes are used.

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References

V. Pless, Introduction to the Theory of Error Correcting Codes, Wiley Student Edition, John Wiley & Sons (Asia) Pte. Ltd., Singapore, (2003).

R. Hill, A First Course in Coding Theory, The Oxford University Press, Oxford, UK, (1986).

W.C. Huffman and V. Pless, Fundamentals of Error Correcting Codes, Cambridge University Press, New York, (2003).

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Published

2015-06-28
CITATION

How to Cite

Rian, A. T., Dey, P. P., & Elora, F. K. (2015). An Investigation of Quaternary [5,3] Error Correcting Codes and their Implementation with Binary Devices. Journal of Informatics and Mathematical Sciences, 7(1), 1–11. https://doi.org/10.26713/jims.v7i1.248

Issue

Vol. 7 No. 1 (2015)

Section

Research Articles

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